Modelling localized charge-injection region of the p-channel low-temperature polycrystalline silicon thin-film transistor

Abstract

The low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is the optimal device for the backplane of the organic light-emitting diode display. At the end the p-channel LTPS TFT fabrication, a charge-injection stress with a strong negative drain bias and a positive gate bias are applied to reduce the off-current by injecting electrons into the gate insulator near the drain. In this study, the charge density and the length of the charge-injection region in the gate insulator were estimated by comparing the measured TFT characteristics with the simulation models with various charge-injection lengths and charge densities. It was found that the effective length of the charge-injection region was 0.96 µm and the charge density was −3 × 1012/cm2 for the 2-µm-channel-length device when VGS was +20 V and VDS was −10 V under the charge-injection stress condition. It was also found, based on the analysis of the electric field distribution under the bias stress condition, that the charge density and the length of the charge-injection region were invariant against the channel length variation. Therefore, the measured TFT characteristics also accorded closely with the simulation models for different channel lengths, such as 4 and 10 µm, when the same characteristic values of the charge-injection region were employed.

Keywords

• LTPS
• thin-film transistor
• polycrystalline silicon
• charge-injection
• GIDL