Journal of Low Power Electronics and Applications (May 2020)

Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips

  • Sriram Vangal,
  • Somnath Paul,
  • Steven Hsu,
  • Amit Agarwal,
  • Ram Krishnamurthy,
  • James Tschanz,
  • Vivek De

DOI
https://doi.org/10.3390/jlpea10020016
Journal volume & issue
Vol. 10, no. 2
p. 16

Abstract

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Aggressive power supply scaling into the near-threshold voltage (NTV) region holds great potential for applications with strict energy budgets, since the energy efficiency peaks as the supply voltage approaches the threshold voltage (VT) of the CMOS transistors. The improved silicon energy efficiency promises to fit more cores in a given power envelope. As a result, many-core Near-threshold computing (NTC) has emerged as an attractive paradigm. Realizing energy-efficient heterogenous system on chips (SoCs) necessitates key NTV-optimized ingredients, recipes and IP blocks; including CPUs, graphic vector engines, interconnect fabrics and mm-scale microcontroller (MCU) designs. We discuss application of NTV design techniques, necessary for reliable operation over a wide supply voltage range—from nominal down to the NTV regime, and for a variety of IPs. Evaluation results spanning Intel’s 32-, 22- and 14-nm CMOS technologies across four test chips are presented, confirming substantial energy benefits that scale well with Moore’s law.

Keywords