A Low-Overhead Timing Monitoring Technique for Variation-Tolerant Near-Threshold Digital Integrated Circuits

Abstract

Near-threshold computing brings several times of magnitude improvement in energy efficiency of digital circuits. However, it also introduces several times of deteriorated delay variations caused by process, voltage, and temperature (PVT) variations. In situ timing monitoring-based adaptive techniques can mitigate excessive timing margins caused by PVT variations, but current frequency and/or voltage tuning methods cause large performance loss. In this paper, we propose a low overhead timing error prediction monitor and a super-fast clock stretching circuit to solve this problem. They are both optimized for near threshold voltage of 0.5 V. When there are timing margins, the frequency will be increased. Until when the timing is intense due to variations, timing monitors will generate a predicted alarm signal. Accordingly, the system clock will be stretched immediately to avoid real timing errors. Applied on a 40-nm CMOS Bitcoin Miner chip, simulation results show that the whole system operating at near-threshold voltage can increase the frequency to up to 2.1× compared with the original non-monitored circuit. Our method can increase the energy efficiency to mitigate near-threshold variations effectively.

Keywords

• Timing monitor
• near-threshold
• clock stretching
• adaptive frequency scaling
• low power