Challenges for 10 nm MOSFET process integration

Abstract

An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. The need for high-k gate dielectrics and a metal gate electrode is discussed. Different techniques for strain-enhanced mobility are discussed. As an example, ultra thin body SOI devices with high mobility SiGe channels are demonstrated.

Keywords

• sstrained silicon
• silicon germanium
• silicon-oninsulator (SOI)
• high-k dielectrics
• hafnium oxide
• nano-wire