Journal of Engineering Science and Technology Review (Aug 2017)

Design of a Low - power CMOS Level Shifter for Low - delay SoCs in Silterra 0.13 μm CMOS Process

  • Mohammad Torikul Islam Badal,
  • Mamun Bin Ibne Reaz,
  • Araf Farayez,
  • Siti A. B. Ramli,
  • Noorfazila Kamal

DOI
https://doi.org/10.25103/jestr.104.02
Journal volume & issue
Vol. 10, no. 4
pp. 10 – 15

Abstract

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