Design and implementation of UVM verification platform based on C_Model

Abstract

As the scale and complexity of integrated circuits increase, the verification work becomes more and more complex and important. The verification cycle has reached or exceeded 70% of the entire chip design cycle. Therefore, it is urgent to find an efficient verification method to improve verification efficiency and enhance reusability of the verification platform. The UVM verification methodology based on the SystemVerilog language can effectively improve the verification efficiency and shorten the verification cycle. Therefore, this paper uses the high-level abstract model C_Model as the reference model to access the UVM platform, verify the encoding module of the tag transmission link in the digital baseband processing unit, design random and non-random testcase, and send it through the driver and monitor verification components. Monitor and collect data, including the data generated by the hardware design RTL code and the data generated by the reference model, and then send the two data to the designed UVM scoreboard module for comparison, thereby verifying the function of the RTL and verifying the pros and cons of the system. It can be reflected by functional coverage. The verification results show that the alignment is correct and the functional coverage reaches 100% in the UVM scoreboard.

Keywords

• systemverilog
• uvm
• c_model
• functional coverage