A 0.2~3.8-GHz Full-Duplex Receiver With More Than 25 dB Self-Interference Cancellation Using a C-DAC-Based Vector Canceller

Abstract

This paper presents a $0.2\sim 3.8$ -GHz in-band (IB) full-duplex (FD) mixer-first receiver based on a vector self-interference (SI) canceller. To ensure the wideband orthogonality of the reconstructed SI signal while minimizing the noise figure (NF) degradation in FD mode, a low insertion loss two-stage polyphase filter (PPF) with a lacking resistance and capacitance (LRC) structure is used in the SI canceller. A 6-bits passive capacitor digital to analog converter (C-DAC) attenuator not only realizes the high-precision amplitude adjustment of the reconstructed SI signal but also avoids the linearity limitation of the back-end modules of the canceller and reduces the noise contribution of the front-end modules at the canceller output. A four-phase mixer-first receiver with enhanced out-of-band (OOB) interference suppression is designed to provide sufficient linearity to reduce the SI-induced nonlinear distortion. As a proof of concept, a prototype FD receiver is fabricated in CMOS 65 nm technology and measured in chip-on-board (COB) package. Measurement results show that it can operate in the frequency range of $0.2\sim 3.8$ -GHz with more than 25 dB SIC amount for 10 MHz bandwidth (BW) 64-QAM modulated signals in fixed (30 dB) channel attenuation test setup. The receiver achieves OOB input-referred third-order intercept point (OOB-IIP3) of +24 dBm and OOB input-referred second-order intercept point (OOB-IIP2) of +82 dBm at 1-GHz local oscillator (LO) frequency. In FD mode, the NF degradation is $\leqslant 1.5$ dB. The effective IB-IIP3 and effective IB-IIP2 are enhanced by 15 dB and 28 dB, respectively. The power consumption of entire FD receiver including the SI canceller is less than 44 mW. The active chip area is 0.55 mm2.

Keywords

• Full-duplex (FD)
• mixer-first
• receiver (RX)
• self-interference cancellation