ParaTM: Transparent Embedding of Hardware Transactional Memory for Traditional Applications

Abstract

As the many-core processors become more prevalent, the parallelism degree of applications is rapidly increasing. It is well known that multi-thread approaches are an effective solution to improve performance by exploiting multiple cores. However, the synchronization problem that occurs between multiple threads can limit the concurrency and scalability of applications. Hardware transactional memory (HTM) has been studied to simplify the synchronization problem, and Intel adopted transactional synchronization extensions (TSX) for its processors in the year 2012. TSX can dynamically decide and perform instructions as an atomic transaction. In this paper, we evaluate and analyze the performance of TSX. It is expected that the latest technology implementing HTM to cope with synchronization scalability will be a nice solution for handling the high degree of parallelism. We found two major reasons that cause performance degradation and propose a novel approach to address these more effectively based on our analysis. We also introduced a mechanism, named ParaTM, to transparently adopt TSX for existing lock-based applications. By using ParaTM, one can apply TSX features without modification of the code. From our evaluation using a micro-benchmark and real-world applications, we confirmed ParaTM is highly effective for transparency and performance. ParaTM achieved 1.75 $\times$ , 4.76 $\times$ , and 1.53 $\times$ better performance compared to the traditional lock mechanism for LevelDB, RocksDB, and Memcached, respectively.

Keywords

• Intel TSX
• synchronization
• transactional memory
• scalability