Check-Bit Region Exploration in Two-Dimensional Error Correction Codes

Abstract

The diversity of nanosatellite applications is increasingly attracting the scientific community’s attention. The main component of these satellites is the OnBoard Computer (OBC), which is responsible for all control and processing. Also, OBC encompasses memory elements highly susceptible to failure; due to spatial radiation, errors in these memories can cause severe damage. As integrated circuit technology advances, cluster errors are more and more frequent. Error Correction Code (ECC) is one of the most used techniques for mitigating errors, and two-dimensional ECCs are used to reach higher error correction power. The paper aims to assess the number of checkbit regions to include for code enhancement. Our analysis investigates the impact of incorporating up to three checkbit regions. The results are analyzed through adjacent and exhaustive error injection tests and compared to other ECCs. Besides, reliability, redundancy, and hardware implementation costs are investigated, and an evaluation metric is proposed to choose the best ECC. Experiments with random error patterns show that the proposal with three crossed check-bit regions achieves a correction of 100% for up to four bitflips and greater than 90% for up to seven bitflips. Additionally, considering adjacent error patterns, the proposal achieves a correction greater than 97.4% with up to five bitflips.

Keywords

• Error correction codes
• fault tolerance
• reliability
• aerospace testing