Robustness Improvement of Single-Phase Inverters Under Weak Grid Cases by Adding Grid Current Feedforward in Delay-Based Phase-Locked Loop

Abstract

For inverters, a phase-locked loop (PLL) is usually needed for the grid synchronization. Typically, for the single-phase inverters, the orthogonal-signal-generators based PLLs (e.g., delay-based PLL) can be used. However, if the grid at the point of common coupling (PCC) exhibits a large grid impedance, the inverter may not work well or even be unstable. In order to work satisfactorily in the very weak grid, this study aims to formulate a robust PLL. At first, by modeling the inverter output impedance and considering the frequency coupling effect, the stability of the typical delay-based PLL has been analyzed and the reason for the performance degradation has been explained. Then, based on analyzing the differences of PLL blocks under different PCC conditions, the robust PLL with the grid current feedforward is discussed. Compared with the typical PLL, the improvement of the system behaviors in the weak grid cases is mainly attributed to the extra term on the numerator of output impedance, which is introduced by the current feedforward of the proposed PLL. The selection of control parameters has been emphasized for maintaining the high robustness. At last, selected comparative waveforms have verified that the single-phase inverter can perform well even with the large grid impedance, without the grid impedance estimation.

Keywords

• Inverters
• phase-locked loops
• grid impedance
• harmonic distortion
• robustness