Characterization of Programmable Charge-Trap Transistors (CTTs) in Standard 28-nm CMOS for Nonvolatile Memory and Analog Arithmetic Applications

Abstract

In this article, we characterized the charge trapping and detrapping behaviors of charge-trap transistors (CTTs) in standard 28-nm CMOS technology and formulated its programmable threshold voltage ( $V_{\mathrm {TH}}$ ). Both thin-oxide and thick-oxide CTT devices are measured, modeled, and analyzed. More than 50- and 100-mV continuous $V_{\mathrm {TH}}$ tuning ranges are achieved for thin and thick oxide devices, respectively. Multiple cycles of programming and erasing operations are demonstrated; however, the reliability needs to be solved in the future. To utilize the developed programmable threshold model, a nonvolatile memory (NVM) cell and an analog arithmetic unit (AAU) are proposed and simulated as two proof-of-concept CTT-based designs.

Keywords

• Analog arithmetic unit (AAU)
• charge trapping/detrapping
• charge-trap transistor (CTT)
• nonvolatile memory (NVM)
• programmable threshold voltage