Cryogenic Embedded System to Support Quantum Computing: From 5-nm FinFET to Full Processor

Abstract

Quantum computing can enable novel algorithms infeasible for classical computers. For example, new material synthesis and drug optimization could benefit if quantum computers offered more quantum bits (qubits). One obstacle for scaling up quantum computers is the connection between their cryogenic qubits at temperatures between a few millikelvin and a few kelvin (depending on qubit type) and the classical processing system on chip (SoC) at room temperature ($300 \,\mathrm{K}$). Through this connection, outside heat leaks to the qubits and can disrupt their state. Hence, moving the SoC into the cryogenic part eliminates this heat leakage. However, the cooling capacity is limited, requiring a low-power SoC, which, at the same time, has to classify qubit measurements under a tight time constraint. In this work, we explore for the first time if an off-the-shelf SoC is a plausible option for such a task. Our analysis starts with measurements of state-of-the-art 5-nm fin-shaped field-effect transistors (FinFETs) at 10 and $300 \,\mathrm{K}$. Then, we calibrate a transistor compact model and create two standard cell libraries, one for each temperature. We perform synthesis and physical layout of a RISC-V SoC at $300 \,\mathrm{K}$ and analyze its performance at $10 \,\mathrm{K}$. Our simulations show that the SoC at $10 \,\mathrm{K}$ is plausible but lacks the performance to process more than a few thousand qubits under the time constraint.

Keywords

• Cryogenic CMOS
• 5-nm fin-shaped field-effect transistor (FinFET)
• hyperdimensional computing
• machine learning classification
• quantum computing
• system on chip (SoC)