Studies of Performance of Cs<sub>2</sub>TiI<sub>6−X</sub>Br<sub>X</sub> (Where x = 0 to 6)-Based Mixed Halide Perovskite Solar Cell with CdS Electron Transport Layer
Kunal Chakraborty,
Nageswara Rao Medikondu,
Kumutha Duraisamy,
Naglaa F. Soliman,
Walid El-Shafai,
Sunil Lavadiya,
Samrat Paul,
Sudipta Das
Affiliations
Kunal Chakraborty
Advanced Materials Research and Energy Application Laboratory, Department of Energy Engineering, North-Eastern Hill University, Shillong 793022, India
Nageswara Rao Medikondu
Department of Mechanical Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram 522302, India
Kumutha Duraisamy
Department of Biomedical Engineering, KarpagaVinayaga College of Engineering and Technology, Chengalpattu 603308, India
Naglaa F. Soliman
Department of Information Technology, College of Computer and Information Sciences, Princess Nourah Bint Abdulrahman University, P.O. Box 84428, Riyadh 11671, Saudi Arabia
Walid El-Shafai
Security Engineering Lab, Computer Science Department, Prince Sultan University, Riyadh 11586, Saudi Arabia
Sunil Lavadiya
Department of Information and Communication Technology, Marwadi University, Rajkot 360003, India
Samrat Paul
Advanced Materials Research and Energy Application Laboratory, Department of Energy Engineering, North-Eastern Hill University, Shillong 793022, India
Sudipta Das
Department of Electronics & Communication Engineering, IMPS College of Engineering and Technology, Malda 732103, India
The present research work represents the numerical study of the device performance of a lead-free Cs2TiI6−XBrX-based mixed halide perovskite solar cell (PSC), where x = 1 to 5. The open circuit voltage (VOC) and short circuit current (JSC) in a generic TCO/electron transport layer (ETL)/absorbing layer/hole transfer layer (HTL) structure are the key parameters for analyzing the device performance. The entire simulation was conducted by a SCAPS-1D (solar cell capacitance simulator- one dimensional) simulator. An alternative FTO/CdS/Cs2TiI6−XBrX/CuSCN/Ag solar cell architecture has been used and resulted in an optimized absorbing layer thickness at 0.5 µm thickness for the Cs2TiBr6, Cs2TiI1Br5, Cs2TiI2Br4, Cs2TiI3Br3 and Cs2TiI4Br2 absorbing materials and at 1.0 µm and 0.4 µm thickness for the Cs2TiI5Br1 and Cs2TiI6 absorbing materials. The device temperature was optimized at 40 °C for the Cs2TiBr6, Cs2TiI1Br5 and Cs2TiI2Br4 absorbing layers and at 20 °C for the Cs2TiI3Br3, Cs2TiI4Br2, Cs2TiI5Br1 and Cs2TiI6 absorbing layers. The defect density was optimized at 1010 (cm−3) for all the active layers.
