A Highly-Efficient and Tightly-Connected Many-Core Overlay Architecture

Abstract

The technology advances of CPU (Central Processing Unit) architecture alternate between generalization and specialization. In the past decade, the general performance has been enhanced while addressing the new brick walls that include power, memory, and ILP (Instruction-Level Parallelism). Thus, it will enter into the era of specialization called adaptable ISA (Instruction Set Architecture) for target applications. Reconfigurable devices such as FPGAs (Field Programmable Gate Array) can offer a solution if the two following issues are addressed. One is the FPGA design is not easy for non-hardware experts, and the other is the process is iterative and lengthy. The most apparent solution to those problems is an overlay that can abstract hardware details while providing a software-like interface. This article presents DRAGON (Dynamically Re-programmable Architecture of Gather-scatter Overlay Nodes), demonstrates its general aspects as well as the way it can be seamlessly integrated into any heterogeneous computing platform. The experimental evaluation of DRAGON reports more than four times better computational efficiency when compared to an Intel Core i9 CPU, in two stencil-based benchmarks.

Keywords

• EPR
• FPGA
• ISA
• many-core
• overlay architecture
• power-efficiency