A triple-level cell charge trap flash memory device with CVD-grown MoS2

Minkyung Kim; Eunpyo Park; Jongkil Park; Jaewook Kim; YeonJoo Jeong; Suyoun Lee; Inho Kim; Jong-Keuk Park; Sung-Yun Park; Joon Young Kwak

Results in Physics (Jul 2022)

A triple-level cell charge trap flash memory device with CVD-grown MoS2

Minkyung Kim,
Eunpyo Park,
Jongkil Park,
Jaewook Kim,
YeonJoo Jeong,
Suyoun Lee,
Inho Kim,
Jong-Keuk Park,
Sung-Yun Park,
Joon Young Kwak

Affiliations

Minkyung Kim: Center for Neuromorphic Engineering, Korea Institute of Science and Technology (KIST), Seoul 02792, South Korea
Eunpyo Park: Center for Neuromorphic Engineering, Korea Institute of Science and Technology (KIST), Seoul 02792, South Korea
Jongkil Park: Center for Neuromorphic Engineering, Korea Institute of Science and Technology (KIST), Seoul 02792, South Korea
Jaewook Kim: Center for Neuromorphic Engineering, Korea Institute of Science and Technology (KIST), Seoul 02792, South Korea
YeonJoo Jeong: Center for Neuromorphic Engineering, Korea Institute of Science and Technology (KIST), Seoul 02792, South Korea
Suyoun Lee: Center for Neuromorphic Engineering, Korea Institute of Science and Technology (KIST), Seoul 02792, South Korea
Inho Kim: Center for Neuromorphic Engineering, Korea Institute of Science and Technology (KIST), Seoul 02792, South Korea
Jong-Keuk Park: Center for Neuromorphic Engineering, Korea Institute of Science and Technology (KIST), Seoul 02792, South Korea
Sung-Yun Park: College of Engineering, Electronics Engineering, Pusan National University, Busan 46241, South Korea; Corresponding authors.
Joon Young Kwak: Center for Neuromorphic Engineering, Korea Institute of Science and Technology (KIST), Seoul 02792, South Korea; Division of Nanoscience and Technology, Korea University of Science and Technology (UST), Daejeon 34113, South Korea; Corresponding authors.

Journal volume & issue: Vol. 38
p. 105620

Abstract

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This study investigates the triple-level cell (TLC) memory retention of a MoS2-channel based charge trap flash (CTF) device. A top-gated CTF device with a high-κ gate dielectric is found to have a high coupling ratio, which enhances the tunneling efficiency for programming. The fabricated devices show the long memory retention performance for each state, demonstrating the feasibility of a robust TLC CTF memory device based on a CVD grown 2D material.

Published in Results in Physics

ISSN: 2211-3797 (Online)
Publisher: Elsevier
Country of publisher: Netherlands
LCC subjects: Science: Physics
Website: http://www.journals.elsevier.com/results-in-physics/

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