Performance Improvement of Spacer-Engineered N-Type Tree Shaped NSFET Toward Advanced Technology Nodes

Abstract

Tree-shaped Nanosheet FETS (NSFET) is the most dependable way to scale down the gate lengths deep. This paper investigates the 12nm gate length (LG) n-type Tree-shaped NSFET with the gate having a stack of high- $k$ dielectric (HfO2) and SiO2 using different spacer materials, which can be done using TCAD simulations. The Tree-shaped NFET device with ${\mathrm {T}}_{\mathrm {(NS)}} =5$ nm, ${\mathrm {W}}_{\mathrm {(NS)}} =25$ nm, ${\mathrm {W}}_{\mathrm {IB}} =5$ nm, and ${\mathrm {H}}_{\mathrm {IB}} =25$ nm has high on-current ( $I_{ON}$ ) and low off-current ( $I_{OFF}$ ). The 3D device with single- $k$ and dual-k spacers are compared and its DC characteristics are shown. It is noted that the dual- $k$ device achieves the maximum $I_{ON}/I_{OFF}$ ratio, which is $10^{9}$ , compared to $10^{7}$ because the fringing fields with spacer dielectric lengthen the effective gate length. Additionally, the impact of work function, interbridge height, width, gate lengths, and temperature, along with the device’s analog/RF and DC metrics, is also investigated in this paper. Even at 12 nm LG, the proposed device exhibits good electrical properties with DIBL =23 mV/V and SS =62 mV/dec and switching ratio ( $I_{ON}/I_{OFF}) = 10^{9}$ . The device’s performance confirms that Moore’s law holds even for lower technology nodes, allowing for further scalability.

Keywords

• Single-k spacer
• dual-k spacer
• tree-shaped NSFET
• nanosheet
• spacer engineering