Accumulator based BIST using Approximate Adders

Abstract

In this paper, we present an accumulator based built-in self test (BIST) with approximate adders for single input change (SIC) test pattern generation. The SIC pairs of test pattern is the key requirement for testing robustly detectable delay faults. The accumulator is designed using approximate adder which is commonly applicable for error tolerant applications whose inputs are driven by barrel shifter. The experimental results show that proposed accumulator with approximate adder is a promising solution for test pattern generation in accumulator based BIST. It is also shown that, the proposed scheme achieves significant reduction in transistor count and generates SIC pairs within (n+1/2) 2n clock cycles as compared to conventional methods.

Keywords

• BIST
• Test pattern generation
• accumulator
• delay fault