A power-efficient pipeline based clock gating FIFO for a dual ported memory array

Abstract

A FIFO is a special type of buffer that controls the data flow between the sender and receiver. It is used to monitor the serial data flow and to avoid mismatch conditions. In general, the dual-ported memory cell array suffers from dynamic power dissipation. In this research article, a 128 x 128-bit Synchronous First-In-First-Out (FIFO) buffer is designed for dual-ported memory cell array with pipeline architecture using clock gating technique, which reduces power dissipation significantly. The FIFO-based dual-ported memory cell array will store a large amount of data and minimize the clock skew. A circular FIFO used in dual-ported memory is organized in a circular queue fashion with two pointers for write and read. Conventional FIFO designs use more power and hardware area on the silicon chip. The FIFO-based pipelining and clock gating approach will improve throughput while reducing dynamic power. The proposed FIFO design is simulated and implemented using the CadenceEncounter tool using 180nm and 45nm Technology. The parameters power consumption, cell utilization, and clock frequency have been analyzed. The synchronous FIFO design reduces the area by 70.3%, power dissipation by 10.6%, and operates at clock frequency up to 322 MHz.

Keywords

• synchronous fifo
• pipeline
• clock gating
• read
• write