Design and Simulation of Reversible Logic Gate Using HCS Macro-Model

Abstract

—Reversible Logic Gates have become very popular for their uninhibited merits like, low power consumption, low garbage output, decreasing the quantum cost, least propagation delay etc. Several circuits have been designed for reversible logic ICs using conventional CMOS technology. But, as the CMOS technology is suffering from scaling down problems, the researchers have moved themselves towards post CMOS devices for further fabrication of Reversible ICs. Among different post CMOS devices, in SET, electrons are tunnelling through the channel one by one, so it offers ultra-low power dissipation compared to the traditional CMOS though it has high speed, high gain like properties. So the hybridization of CMOS-SET can achieve a useful effect on VLSI design, and the new technology is known as Hybrid CMOS-SET (HCS). But as the Hybrid CMOS-SET requires two distinct software, the HCS macro model has become very useful, as it can be simulated by using a single software. In this present paper, the reversible logic gate has been designed using the HCS macro model and is also being simulated using a single software, MATLAB with SIMULINK, with low power consumption.

Keywords

• Reversible Logic Gate
• CMOS
• Single electron transistor
• Hybrid CMOS SET
• Macro model