Cybernetics and Information Technologies (Mar 2014)

Towards a design space exploration methodology for system-on-chip

  • Chariete A.,
  • Bakhouya M.,
  • Gaber J.,
  • Wack M.

DOI
https://doi.org/10.2478/cait-2014-0008
Journal volume & issue
Vol. 14, no. 1
pp. 101 – 111

Abstract

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This paper provides an overview of a design space exploration methodology for customizing or tuning a candidate OCI architecture, given a resources budget and independent of a particular application traffic pattern. Three main approaches are introduced. The first approach allows customizing the On- Chip Interconnect by adding strategic long-rang links, while the second consists in customizing the buffer sizes at each switch according to the traffic. The third approach uses a feedback control-based mechanism for dynamic congestion avoidance. Some results are presented to shed more light on the usefulness of these approaches for System-on-Chip design.

Keywords