Results in Control and Optimization (Dec 2023)
Empowering energy with a cutting-edge reversible logic framework for universal shift registers
Abstract
In order to meet the increasing need for reduced power consumption, reduced circuit size, and increased operating speed, this research focuses on the efficient design of reversible shift registers. The shift register is an essential building block of both arithmetic logic units (ALUs) and reversible memory circuits. In this research, an improved layout is shown for a variety of shift register types, including those with serial input and parallel output (SIPO), serial input and serial output (SISO), parallel input and parallel output (PIPO), parallel input and serial output (PISO), and universal shift registers (USR). Our approaches lessen waste in compared to standard procedures by maximizing '0′ GO and reducing CI. The 4-bit SIPO register has a 70 % increase in CI performance over previous designs and also provides SISO capability with a 50 % CI and 100 % GO boost. Our proposed designs for the SIPO, SISO, PIPO, and PISO registers also result in a 70 % and 80 % improvement in CI and GO for the 4-bit PISO register. We enhance the 4-bit Universal Shift Register (USR) design by 62.5 % in CI, 50 % in CI, 12.5 % in GO, and 56.25 in GO over the previous design.
