Implementation of Individual and Combined In-loop Filters for HEVC and AVC Video Coding Standards on ASIC Platform Using 32 nm Technology Library

Abstract

High Efficiency Video Coding (HEVC) and Advanced Video Coding (AVC), the developed international standards for video compression, offer significantly better video compression efficiency. However, there are some similarities in the in-loop filtering algorithms which can be combined and implemented in a design. By evaluating the similarities in in-loop filtering algorithms of HEVC and AVC, a combined in-loop filter is designed to evaluate its implementation cost and performance with respect to individual AVC and HEVC in-loop filters. The in-loop filters of three designs are used to process the pixels in a stream of 64×64 blocks. The proposed combined design is implemented in Verilog. The Verilog RTL code is verified in application specific integrated circuit (ASIC) platform using 32 nm technology library and Synopsys EDA tools. Experimental results illustrate that the proposed combined in-loop filters reduce the total resources utilization of individual in-loop filters by 20% in terms of total cell area. In comparison to the individual HEVC in-loop filter design, which is greater than the individual AVC in-loop filter design, the unified design consumed just 0.38 times power consumption overhead.

Keywords

• advanced video coding
• high efficiency video coding
• in-loop filters
• video compression