Design and implementation of parallel CRC algorithm for fibre channel on FPGA

Abstract

Fibre channel (FC) provides the high-speed and low-latency communication between the end systems, widely used in data storage, aerospace applications and large electronic equipment including radar systems. Excellent in error detection and easy to be implemented in hardware, cyclic redundancy check (CRC) is an important error detection method widely used in network data transmission. This study introduces a design and development of parallel CRC algorithm for the hardware implementation on FPGA to meet the specifications for FC. The algorithm can process 128-bit parallel data in a block by broken it into four 32-bit data and calculate their CRC, respectively, based on the linear feedback shift register, simplifying the calculation process and reducing resource consumption.

Keywords

• error detection
• field programmable gate arrays
• shift registers
• cyclic redundancy check codes
• parallel crc algorithm
• fibre channel
• fpga
• low-latency communication
• end systems
• data storage
• aerospace applications
• electronic equipment including radar systems
• cyclic redundancy check
• important error detection method
• network data transmission
• hardware implementation
• 128-bit parallel data
• 32-bit data