An Ultra-Low-Voltage Level Shifter With Embedded Re-Configurable Logic and Time-Borrowing Latch Technique

Abstract

The increasing number of voltage domains along with the size of the data bus requires an exponential increase in the number level shifter (LS) circuits for signal interfacing, creating an exploding in silicon area and power consumption. Higher area-efficiency can be attained by further improving the integration density of the LS circuit. In this paper, we present a multi-function ultra-low-voltage LS with re-configurable logic with embedded time-borrowing latch. The proposed circuit is implemented on CMOS 45nm technology. It is capable of converting the input voltage of 0.3 V to an output voltage of 1.8 V with an input frequency of 1 MHz. The proposed architecture has achieved a superior area efficiency with reduced transistors number of $2.4\times $ and reduced power delay product (PDP) of $4.65\times $ compared with its discrete logic block level implementation when the input voltage, output voltage, and the input frequency are 0.3 V, 1.8 V, and 1 MHz, respectively. The average propagation delay and power consumption are 52.7 ns and 34.6 nW, respectively.

Keywords

• Level shifter
• ultra-low-voltage
• embedded re-configurable logic
• time-borrowing latch technique