1.2‐kV silicon carbide planar split‐gate MOSFET with source field plate for superior figure‐of‐merits

Abstract

Abstract Planar split‐gate MOSFETs (SG‐MOSFETs) are promising in high‐frequency power applications due to the fast turn on/off speeds and low switching loss. However, SG‐MOSFETs suffer from crowded electric field at the edge of the split poly‐Si gate, resulting in the degradation of the blocking voltage and the gate oxide reliability. This issue becomes more critical in 4H‐SiC MOSFETs due to the high critical breakdown electric field. In this work, a new 1.2‐kV 4H‐SiC SG‐MOSFET structure is proposed and investigated by TCAD simulation. The proposed structure features a source metal field plate located between two adjacent split poly‐Si gates (termed SFP‐SG‐MOSFET). In the blocking state, the source metal field plate reduces the peak electric field at the edge of the poly‐Si gate. The maximum electric field in the gate oxide of the proposed SFP‐SG‐MOSFET is reduced by 52.8% compared with the SG‐MOSFET, for reliable operation. The reverse transfer capacitance (Crss) and gate‐to‐drain charge (Qgd) are reduced by 56.4% and 61.8% compared with SG‐MOSFETs, respectively. Therefore, the high‐frequency figure‐of‐merits (HF‐FOM) [Ron × Crss] and [Ron × Qgd] are improved by 2.2 times and 2.5 times, respectively.