Quenching Circuit and SPAD Integrated in CMOS 65 nm with 7.8 ps FWHM Single Photon Timing Resolution

Abstract

This paper presents a new quenching circuit (QC) and single photon avalanche diode (SPAD) implemented in TSMC CMOS 65 nm technology. The QC was optimized for single photon timing resolution (SPTR) with a view to an implementation in a 3D digital SiPM. The presented QC has a timing jitter of 4 ps full width at half maximum (FWHM) and the SPAD and QC has a 7.8 ps FWHM SPTR. The QC adjustable threshold allows timing resolution optimization as well as SPAD excess voltage and rise time characterization. The adjustable threshold, hold-off and recharge are essential to optimize the performances of each SPAD. This paper also provides a better understanding of the different contributions to the SPTR. A study of the contribution of the SPAD excess voltage variation combined to the QC time propagation delay variation is presented. The proposed SPAD and QC eliminates the SPAD excess voltage contribution to the SPTR for excess voltage higher than 1 V due to its fixed time propagation delay.

Keywords

• single photon avalanche diode
• quenching circuit
• single photon timing resolution
• SiPM
• 3D digital silicon photomultiplier
• 3D integrated detector
• time-of-flight
• positron emission tomography