FPGA Implementation of SSRS Codes for NAND Flash Memory Device

Abstract

NAND flash memory is a non-volatile storage device that is extensively used in personal electronic gadgets, digital television, digital cameras, and many consumer/ professional electronics devices. Error control coding techniques have been incorporated to improve the integrity of information stored in these devices. We have synthesized the Subfield Subcodes of Reed Solomon codes (SSRS) for use on Multi-Level cell (MLC), Triple Level Cell (TLC), and Quadruple Level Cell (QLC) NAND flash devices. The primary advantage of these codes is that the codeword symbols can be correctly matched to the number of bits that can be stored in these multilevel cells. Deployment of these codes improves the integrity of information storage and useful life. This paper describes the implementation of the encoder and decoder of SSRS codes synthesized for MLC, TLC, and QLC NAND flash devices. The encoder circuit is designed using addition and multiplication tables derived from elements of synthesized SSRS codes. The Non-binary decoding procedure consists of the syndrome computation, Berlekamp -Massey algorithm, Chein search, and Forney’s algorithm. The designed encoder requires 16% resources for MLC, 18% of resources for TLC, and 18% of resources for QLC. This research work has reported the design of very high rate ( $R \geq 0.97$ ) codes that can bring about significant improvements to the Undetected Bit Error Rate (UBER) even when the Raw Bit Error rate (RBER) values are significant ( $\gt 10^{-3}$ ).

Keywords

• Bit error rate
• channel codes
• FPGA
• Galois field
• NAND flash
• reed-Solomon codes