Robust sub-100 nm T-Gate fabrication process using multi-step development

Abstract

We demonstrate the fabrication of sub-100 nm T-Gate structures using a single electron beam lithography exposure and a tri-layer resist stack - PMMA/LOR/CSAR. Recent developments in modelling resist development were used to design the process, in which each resist is developed separately to optimise the resulting structure. By using a modelling approach and proximity correcting for the full resist stack, we were able to independently vary gate length (50-100 nm) and head size (250-500 nm) at the design stage and fabricate these T-Gates with high yield.

Keywords

• Sub-100 nm T-Gate
• Tri-layer resist stack
• Multi-development