A Background Jitter Calibration for ADCs Using TDC Phase Information From ADPLL

Abstract

The phase noise, commonly known as jitter, in Phase-Locked Loops (PLLs) is conventionally perceived as a stochastic process, necessitating a degree of tolerance in downstream circuits such as Analog-to-Digital Converters (ADCs). This paper addresses this issue within the context of a Time-to-Digital Converter (TDC)-based All-Digital Phase-Locked Loop (ADPLL) responsible for generating the sampling clock for ADCs. The ADPLL uses a low-quality, high-noise oscillator while remaining area- and power-efficient. Any jitter introduced in the ADPLL’s clock signal directly causes non-uniform sampling by the ADC. We propose a background all-digital algorithm to address this challenge. The least-square jitter estimation algorithm uses the TDC phase information to detect instantaneous sampling error and a Taylor-based correction is used to perform ADC post-correction. We evaluate the efficacy of these algorithms through extensive simulations, considering a realistic system setup. The overarching system performance is quantified using SNDR as the primary performance metric, demonstrating enhancements of up to 33 dB across the designated operational frequency range when contrasted with uncorrected ADC outputs.

Keywords

• ADC
• jitter calibration
• ADPLL
• non-uniform sampling
• interpolation algorithm
• digital signal processing