Cryo-CMOS modeling and a 600 MHz cryogenic clock generator for quantum computing applications
Qiwen Xue,
Yuanke Zhang,
Mingjie Wen,
Xiaohu Zhai,
Yuefeng Chen,
Tengteng Lu,
Chao Luo,
Guoping Guo
Affiliations
Qiwen Xue
CAS Key Laboratory of Quantum Information, Hefei 230026, China; Department of Microelectronics, University of Science and Technology of China, Hefei 230026, China
Yuanke Zhang
CAS Key Laboratory of Quantum Information, Hefei 230026, China; Department of Physics, University of Science and Technology of China, Hefei 230026, China
Mingjie Wen
CAS Key Laboratory of Quantum Information, Hefei 230026, China; Department of Cyber Science and Technology, University of Science and Technology of China, Hefei 230026, China
Xiaohu Zhai
CAS Key Laboratory of Quantum Information, Hefei 230026, China; Department of Microelectronics, University of Science and Technology of China, Hefei 230026, China
Yuefeng Chen
CAS Key Laboratory of Quantum Information, Hefei 230026, China
Tengteng Lu
CAS Key Laboratory of Quantum Information, Hefei 230026, China; Department of Physics, University of Science and Technology of China, Hefei 230026, China
Chao Luo
CAS Key Laboratory of Quantum Information, Hefei 230026, China; Department of Physics, University of Science and Technology of China, Hefei 230026, China; Corresponding author.
Guoping Guo
CAS Key Laboratory of Quantum Information, Hefei 230026, China; Department of Physics, University of Science and Technology of China, Hefei 230026, China; Department of Microelectronics, University of Science and Technology of China, Hefei 230026, China
The development of large-scale quantum computing has boosted an urgent desire for the advancement of cryogenic CMOS (cryo-CMOS), which is a promising scalable solution for the control and read-out interface of quantum bits. In the current work, 180 nm CMOS transistors were characterized and modeled down to 4 K, and the impact of low-temperature transistor performance variations on circuit design was also analyzed. Based on the proposed cryogenic model, a 180 nm CMOS-based 450 to 850 MHz clock generator operating at 4 K for quantum computing applications was presented. At the output frequency of 600 MHz, it achieved < 4.8 ps RMS jitter with 30 mW power consumption (with test buffer), corresponding to a −211.6 dB jitter-power FOM, which is suitable for providing a stable clock signal for the control and readout electronics of scalable quantum computers.
