Design of small and high efficiency anti radiation seeker receiving scheme

Abstract

In the design of receiving circuit of anti radiation seeker, aiming at the heavy amount of data processing in the back end signal and the complicated connection between analog front end and digital back end, a receiver scheme of seeker based on digital down conversion(DDC) module and JESD204B high speed serial interface is proposed. The scheme adopts modular design idea, and digital down conversion of multi baseband signals is completed in advance in front of the seeker analog front-end, so the amount of data processed at the back of the signal is reduced. Using a new generation of high-speed serial JESD204B interface as analog front-end output, the JESD204B single channel receiver interface has been completed in Xilinx's Kintex-7 series FPGA by means of simulation and analysis JESD204 Phy IP. Through simulation and experiment, it is proved that the designed receiving scheme meets the functional requirements of the anti radiation seeker and has certain advanced characteristics.

Keywords

• JESD204B
• digital down conversion
• baseband separation
• high speed AD