Design of a high-performance and dynamic reconfigurable SPI IP core with master and slave mode

Abstract

To meet the flexible configuration requirements of serial peripheral interface(SPI) in the System-on-a-Chip(SoC), the SPI IP core which can be configured as a master or slave with four date transfer modes and seven clock transmission rates is designed. The SPI IP core through the state machine controls the port direction of data transmission module, which solves the problem of the opposite direction of data transmission in master and slave mode. The SPI IP core also multiplexes the shift register to reduce logic resource consumption. The clock frequency division module is designed to realize the data exchange with different transmission rates. In order to facilitate the operation of the SPI IP core, the ports including cpol and cpha that can configure the data transfer modes are designed. The results show that the SPI IP core is in good agreement with the SPI bus protocol. In addition, the circuit scale contains 1 062 logic gates under the 0.13 μm technology and the power consumption is 0.395 7 mW at a system operating frequency of 80 MHz.

Keywords

• high-performance
• master and slave mode
• dynamic reconfigurable
• serial peripheral interface(SPI)
• IP core