CMOS readout FEE based TV-BLR module for CdZnTe pixel detectors in high count rate applications

Abstract

In this study, a time-variant baseline restorer (TV-BLR) circuit was designed and implemented to address the poor frequency selectivity issue in the shaping units of most state-of-the-art readout electronics for CdZnTe/CdTe detectors used in biomedical imaging applications. The proposed circuit improves image quality by canceling the artifacts that result from poor temporal and energy resolution in PET imaging. The proposed circuit consists of a Charge Sensitive Preamplifier (CSP) followed by a classical pole-zero compensation circuit. Two stages of integrators are added and a frequency rectifier module named the TV-BLR circuit has been built. The open-loop amplifier for the CSP is a single-ended input stage amplifier, designed for low-power applications with a maximum power consumption of 43 µW from a 1.2 V supply voltage, verified through post-layout Monte Carlo simulations. The TV-BLR increases the selectivity of the shaping filter, lowers the equivalent noise charge (ENC), and restores the baseline of the circuit to only 143 µV dc-offset. It also extends the counting rate behavior of the system by handling the time-over-threshold (ToT), which depends on the tail current (Itail) of the comparator stage. The circuit was designed, simulated, and validated for an input dynamic of 2–12.5fC, providing an energy range of 55.1–354.3 keV. The design has a charge-to-voltage conversion factor of 56.7 mV/fC with a 4% non-linearity error for an input detector capacitance of 200 fF, while achieving an optimal ENC of 57.4 e − RMS ± 0.1 e−/fC with 13.27 ns peaking time. Process Voltage Temperature (PVT) analysis was performed to validate the simulation results and performance metrics of the design. The proposed design improves energy resolution and avoids energy losses due to the readout system.

Keywords

• Baseline restorer
• PET
• PVT
• SPECT
• Time-over-Threshold
• and TV-BLR