Reliability assessment of high-power GaN-HEMT devices with different buffers under influence of gate bias and high-temperature tests

Abstract

This study compares Vth-instability in D-mode MIS-HEMT devices between two epitaxial layers, AlN/AlGaN/GaN superlattice-W1, and three-step graded AlGaN-W2. Experimental results demonstrate that W1 exhibits ∼13% less Vth-instability compared to W2, with distinct degradation regions at specific voltage ranges. With temperature variation (30 °C–150 °C), these regions are justified and revealed small positive Vth-shifts due to electron trapping, leading to temporary degradation, followed-by negative Vth-shifts from positive charge injection, culminating in catastrophic degradation attributing impact ionization at 30 °C during 0–30 V gate-step stress, with permanent failure observed. Analysis indicates W1-devices are more efficient and stable. Also, both layers operate reliably till V _GS = 18 V, with ∼3% minor Vth instability.

Keywords

• semiconductor device reliability
• GaN-HEMT
• semiconductor device process
• semiconductor device testing