Intrinsic Evolution of Truncated Puiseux Series on a Mixed-Signal Field-Programmable SoC

Abstract

Mixed-signal system-on-chip (SoC) devices offer single-chip solutions, but face challenges of hardware-software co-design optimization, device signal range constraints, and limited precision. These issues are addressed by developing a multi-level evolutionary approach to realize complex computational circuits called Embedded-Cascaded Hierarchically Evolved Logic Output Networks (ECHELON). The ECHELON technique utilizes analog evolved building blocks and refines their output using digital fabric to compose power series expansions of transcendental functions which are all routed under intrinsic control on a field-programmable SoC (PSoC). The result for the evolution of seven different powers of the independent variable is a reduction of 31.24% in the overall error as compared to the analog circuits that produce the raw inputs to a differential digital correction phase. Computation blocks developed on a Cypress PSoC-5LP mixed-signal SoC reduced error in the final mathematical approximation to the range of 40–150 mV. In doing so, speedups of roughly 1.4-fold to 6.6-fold with an average of 2.72-fold reduction in function execution times were attained. In particular, this approach achieved a 41.7-fold reduction in error with respect to the largest power of the independent variable used as an input to compute an erf(x) function.

Keywords

• Programmable System on Chip (PSoC)
• Power Series
• Genetic Algorithm
• Programmable Logic Device