Towards Improving Clock Domain Crossing Verification for SoCs

Abstract

Moore‘s law has been motivating the semiconductor industry to churn out multi-clock (mostly unrelated) complex system on chip (SoC) designs. Data/signals that crosses such unrelated or asynchronous clock domains are more likely to be sampled before they are stable, and can cause issues like metastability. Such clock domain crossing (CDC) signals must be synchronized between the domains using a valid synchronizer, and must be verified in some way exhaustively before quality sign-off. If not verified appropriately or detected late in the design cycle, these crossings will result into chip re-spins and prove too costly, as sometimes the product itself will be out of market. The typical challenge in flat netlistbased CDC verification checks is huge run time, memory consumption & millions of violations to debug counts. In this paper, therefore, a hierarchical CDC verification methodology has been implemented for system-on-chip integrated circuits. This hierarchical approach improves the CDC verification for SoC in terms of memory consumption, time taken for sign-off without compromising quality.

Keywords

• soc
• metastability
• clock domain crossing
• synchronization
• reset domain crossing
• glitch