Design of an ASIC Digital Clock Using VLSI Technology

Abstract

We present the design of an Application Specific Integrated Circuit (ASIC) digital clock based on the 0.12 µm deep submicron technology node. The widths of the PMOS and NMOS transistors are 0.72 µm and 0.24 µm, respectively. The clock expresses time based on the 12-hour time notation. The gate-level schematic and the layout of the design are drawn and validated using DSCH3 and Microwind3 Lite. The key feature of the clock is constructed from 18 D-type flip-flops. Two modulo-60 counters and a modulo-12 counter are built from the flip-flops. The modulo-60 counters are used for the second and minute modules, while the modulo-12 flip-flop is for the hour module. The length and width of the layout are, respectively, 153.60 µm and 58.14 µm. This is to say that the size of the die is comparable with that of a human hair. The average static power dissipation is found to be 0.202 mW, which is reasonably low. Since the proposed design is in the form of an ASIC chip, the input and output pins merely require to be connected to an external power source, an oscillator, and displays, to allow the clock to operate properly. With its miniaturized size and low power consumption, the proposed design clearly exhibits advantages over those built using discrete components and general-purpose chips.

Keywords

• asic
• deep submicron technology
• digital clock
• modulus counter
• vlsi