Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes

Abstract

Many-tier vertical gate-all-around nanowire FET (VFET) synthesis strongly demands a holistic approach of modeling/formulating/optimizing transistor placement and in-cell routing to obtain the maximum-achievable power, performance, area, and cost (PPAC) benefits. In this article, we propose a novel satisfiability modulo theories (SMT)-based many-tier VFET standard cell (SDC) synthesis framework that simultaneously solves place-and-route (P&R). We devise an extended relative positioning constraint and a dummy gate control scheme to capture the unique VFET cell architecture. Moreover, we present efficient objectives to improve pin-accessibility and reduce the use of vertical routing, which has high resistance. Compared to the conventional sequential P&R approach, our concurrent P&R achieves a 15.2% smaller cell area on average for 2-tier VFET. Throughout the extensive exploration for many-tier VFET configurations up to 4-tier, we show that the 4-tier VFET respectively achieves 50.1% and 27.9% of average area reduction on chip-level and block-level, over 4.5T GAAFET.

Keywords

• Automatic standard cell (SDC) generation
• constraint satisfaction problem (CSP)
• gateall-around (GAA)FET
• pin accessibility
• satisfiability modulo theories (SMT)
• vertical GAA nanowire FET (VFET)