Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems

Abstract

In recent years, memory safety issues in embedded environments have garnered significant attention, with spatial and temporal memory violations in heap memory emerging as critical security threats. To address these challenges, this paper proposes an efficient tag-based memory verification system specifically designed for RISC-V in-order processors. The proposed system integrates a Heap Check Cache (HC-Cache), FIFO Buffer, and Store Head Buffer/Clear Head Buffer (SHB/CHB) with a replay mechanism at the hardware level to minimize performance overhead. On the software side, it incorporates extended RISC-V ISA instructions and a modified Newlib C library to automate metadata management and tag generation without requiring additional modifications to user applications. The system was implemented on an FPGA platform using the Xilinx VC707 board. The implementation results indicate a 16.07% increase in LUTs and a 58.25% increase in Flip-Flops, while maintaining minimal overhead for BRAM (0.66%) and LUTRAM (0.99%). Performance evaluations using workloads such as Mibench, Olden, and SPEC2006 demonstrated a significantly lower average performance overhead compared to previous work. Furthermore, verification using the NIST Juliet Test Suite 1.3 revealed that the system successfully detected 100% of heap-related vulnerabilities, including 1,924 heap-based overflows, 803 double-free errors, and 394 use-after-free errors. These results demonstrate that the proposed system provides high security and performance efficiency, even in resource-constrained embedded environments.

Keywords

• RISC-V
• FPGA
• memory safety
• security