Functional Compaction for Functional Test Sequences

Abstract

The occurrence of silent data corruption because of hardware defects in large scale data centers points to the advantages of applying functional test sequences to detect hardware defects that escape scan-based tests. When using functional test sequences, test compaction is important to avoid excessive numbers of clock cycles of test application. However, test compaction procedures for binary sequences at the gate-level eliminate arbitrary parts of the sequence, and may thus produce a compacted sequence that is not applicable during functional operation. This article makes the counterintuitive observation that by using design-for-testability (DFT) logic, it is possible to restore the functional operation of the circuit after eliminating parts of a sequence with only a limited and short term disruption of functional operation conditions. The article describes a test compaction procedure that inserts DFT logic while compacting a sequence. Experimental results for benchmark circuits demonstrate that significant levels of test compaction can be achieved for many of the benchmark circuits considered. A by-product of test compaction is an increase in the fault coverage.

Keywords

• Design-for-testability (DFT)
• functional test sequence
• test compaction
• test generation