FPGA-Based Multi-Level Approximate Multipliers for High-Performance Error-Resilient Applications

Abstract

This paper presents approximate multipliers which are efficiently deployed on Field Programmable Gate Arrays (FPGAs) by using newly proposed approximate logic compressors at different levels of accuracy. Our approximate multiplier designs offer higher gains of power-delay-area products (PDAP) than those of the state-of-the-art works at comparable accuracies. Furthermore, in terms of delay, occupied area, and dynamic power dissipation, our designs are much better than Lookup Table based multiplier Intellectual Properties that are available on an FPGA. Particularly, our proposed 8-, 16-, and 32-bit multipliers can deliver PDAP gains up to 7.1 x, 8.3 x, and 5.0 x, respectively. The effectiveness and applicability of our designs are also demonstrated by image processing applications such as image multiplication and sharpening. The experiments show that for the image sharpening, our 8 x 8 multipliers can deliver a good peak signal-to-noise ratio (PSNR) of 46.81 dB, a structural similarity index metric (SSIM) of 0.9989, and a dynamic power saving of up to 36.7% with regard to the exact multiplier. For the image multiplication, approximate 16 x 16 multipliers can offer a high PSNR of 80.25 dB, an SSIM of 1.0, and a dynamic power saving of up to 58.15%. From these demonstrations, the proposed multipliers are expected to be appropriate with high-performance and low-power error-resilient applications.

Keywords

• Approximate computing
• approximate compressor
• error-resilient application
• multiplier
• power-delay-area product