A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces

Abstract

Separate inverter-based summers for each eye are introduced into the decision feedback equalizer (DFE) of a single-ended four-level amplitude modulation (PAM-4) receiver for memory interfaces. The summers increase the input swing of the slicers while maintaining the advantages of inverter-based amplifiers with higher gain and lower power consumption than current-mode logic (CML) amplifiers. The high-gain summer can improve clock-to-Q delays of slicers in the PAM-4 DFE without increasing the power consumption of the slicers. This can alleviate the timing constraint that the DFE must meet to respond correctly to the previous data. The non-linear gain of the inverter-based structure can be ignored by using separate paths depending on each eye. A prototype chip was fabricated in a 65 nm CMOS process. At 24 Gb/s, the DFE can achieve a bit error rate (BER) of 10−12 with an eye width of 100 mUI with −7.3 dB insertion loss at Nyquist frequency and the power efficiency of 0.73 pJ/b.

Keywords

• Four-level pulse amplitude modulation (PAM-4) receiver
• inverter-based summer
• memory interface