Improved Real-Time Dynamic Migration Mechanism of Array Processor Data Cache

Abstract

The on-chip distributed storage structure satisfies the high parallelism requirements of the array processor for memory access, and alleviates the problem of memory wall to some extent. However, in the case of remote access, the long latency problem of distributed storage structure is still very severe. Aiming at this problem, an improved real-time dynamic migration mechanism based on distributed data Cache is designed. It uses four-level fully interconnection and migration interconnection to dynamically schedule remote data based on data access frequency, effectively reducing the delay of remote access. Based on the distributed Cache structure of the array processor, the proposed real-time dynamic migration mechanism is verified by parallel implementation of typical algorithms such as motion compensation. The experimental results show that the distributed Cache with the real-time dynamic migration mechanism can provide data access bandwidth up to 10.68 GB/s at the operating frequency of 166.9 MHz. Compared to similar architectures, remote access latency is reduced by 46.5%.

Keywords

• array processor
• distributed cache
• dynamic migration
• cache consistency