Deep Learning-Based Integrated Circuit Surface Defect Detection: Addressing Information Density Imbalance for Industrial Application

Abstract

Abstract In this study, we aimed to address the primary challenges encountered in industrial integrated circuit (IC) surface defect detection, particularly focusing on the imbalance in information density arising from difficulties in data sample collection. To this end, we have developed a new hybrid architecture model for IC surface defect detection (SDDM), based on ResNet and Vision Transformer (ViT). The core innovation of SDDM lies in the integration of the concepts of image information density and dataset information density, effectively identifying and processing areas of high information density through multi-channel image segmentation techniques. The convolution operations performed within each patch of the model help to precisely capture positional information, thereby meticulously differentiating the complex details on the surface defect detection of ICs. We optimized the model to make it more suitable for industrial applications, significantly reducing computational and operational costs. The experimental results confirmed that the improved SDDM model achieved an accuracy rate of 98.6% on datasets with uneven information density, effectively enhancing the productivity of IC packaging and testing companies, particularly in handling datasets with imbalanced information density.

Keywords

• Deep learning
• Defect detection
• Integrated circuit
• Intelligent manufacturing