In order to utilize perpendicular spin-torque-transfer magnetic-random-access-memory (p-STT MRAM) as a storage class memory, the achievement of performing multi-level-cell (MLC) operation is important in increasing the integration density of p-STT MRAM. For a double pinned perpendicular magnetic tunneling junction spin-valve performing MLC (i.e., four-resistance level) operation, the uniformity in the resistance difference between four-level resistances was investigated theoretically and experimentally. The uniformity in the resistance difference between four-level resistances was strongly dependent on the top MgO tunneling-barrier thickness. Particularly, the most uniform resistance difference between four resistance states could be achieved at a critical top-MgO tunneling thickness (i.e., ∼1.15 nm).
