A 1.2V, low-power, and high linear UWB down-conversion CMOS mixer

Abstract

A low voltage, high linearity and gain withlow powerultra-wideband (UWB) CMOS mixer in the RF receiver is proposed. This mixer is designed for a standard of 802.11 for use in Wi-Fi communications. The linearization technique for the third-order transconductance (푔푚3) cancellation with modified derivativesuperposition (MDS) is utilized to enhance the linearity performance of the proposed mixer. The MDS technique employs anauxiliary PMOS transistor in parallel with the NMOS transistor in the lower tree (transconductance stage)for reducing the third-orderintermodulationdistortion (IMD3).Besides, a switched buffer stage and the active loads are employed to improve the conversion gain of the mixer. High gain and high linear mixer is designed by the MDS technique and switched buffer. The proposed mixer is analyzed, and simulated using a 0.18 μm CMOS TSMC process; The LNA achieves 9.1dB conversion gain, maximum input third-order intercept point (IIP3) of +15dBm, double side-band noise figure (DSB NF) of 15.6 dB. This module consumes 2.06 mW DC power from a 1.2 V power supply in the RF frequency of 10 GHz.

Keywords

• cmos
• linearity
• low voltage mixer
• conversion gain
• switched buffer