An Innovated 80V-100V High-Side Side-Isolated N-LDMOS Device

Abstract

We used TCAD Synopsys 3D tools and device simulators to propose an innovative device structure of 80V-100V high-side NLDMOS by using the silicon to silicon-di-oxide ratio with side trench. The high-side can also be developed by placing an NBL structure which can deliver a high as over 200V isolation voltage. The 3D structure can clear see the optimized linear p-top and n-drift region have better charge balance with linear doping profile to get the benchmark breakdown voltage (BVdss) of 80V with on-resistance (Ron) as low as 130 mΩ-mm2 and 100V with on-resistance as low as 175 mΩ-mm2.The linear p-type buried layer using high dosage and lower energy to achieve the better SOA and higher isolation voltage. Optimized linear p-top and PBL can improve Ron by 32.5% compare to other 100V high side device which have done from reference.