High-Performance and Area-Efficient Ferroelectric FET-Based Nonvolatile Flip-Flops

Abstract

Recently, nonvolatile systems with nonvolatile flip-flops (NVFFs) have gained prominence for their energy efficiency in energy-harvesting devices and battery-operated Internet of Things applications. They are normally-off instantly-on, and thus, can save energy effectively owing to their zero standby power consumption. An NVFF stores the computing state in nonvolatile memories (NVMs) when the power is off. A ferroelectric field-effect transistor (FeFET) is one of the most promising NVMs owing to its high $\text{I}_{\mathrm {on}}/\text{I}_{\mathrm {off}}$ ratio and low write power. Three FeFET-based NVFFs (previous FeFET-out NVFF-1/-2 and FeFET-in NVFF) were recently proposed to improve the area, power, and speed; however, they still have their own problems. Previous FeFET-out NVFF-1 has large area overhead and previous FeFET-out NVFF-2 does not properly perform restore operation. Previous FeFET-in NVFF has a long clock-to-Q delay and high operating energy. This paper introduces two novel FeFET-based NVFFs (proposed FeFET-out and -in NVFFs). Proposed FeFET-out NVFF reduces the large area overhead of previous FeFET-out NVFF-1 and corrects the malfunction in the restore operation of previous FeFET-out NVFF-2. Proposed FeFET-in NVFF achieves a better clock-to-Q delay, operating energy, and area than the previous FeFET-in NVFF. Monte Carlo simulations based on an industry-compatible 10-nm FinFET model are performed for a comparative analysis. Proposed FeFET-out NVFF achieves 17.6% smaller area with slightly higher (6.3%) operating energy and only 0.8% slower clock-to-Q delay than previous FeFET-out NVFF-1. Proposed FeFET-in NVFF achieves 18.9% shorter clock-to-Q and 3.0% smaller operating energy with 8.7% smaller area than the previous FeFET-in NVFF.

Keywords

• Energy harvesting
• ferroelectric field-effect transistor
• hysteresis
• Internet of Things
• nonvolatile flip-flop
• power gating