Journal of Engineering and Sustainable Development (Jun 2006)

Design and Implementation of JPEG 2000 Image Compression using FPGA

  • Munther N. B. Al-Tikriti,
  • Dhafer R. Z. Al-Rawi,
  • Ienas F. Y. Iskander

Journal volume & issue
Vol. 10, no. 2

Abstract

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This paper investigates the use of a Field Programmable Gate Array (FPGA Xilinx Virtex-II) to perform hardware implementation for low speed part of JPEG2000 to achieve a real time JPEG2000 system. In this paper multi processes modules written in the VHDL is proposed that can be used to accelerate an existing software implementation of JPEG2000.

Keywords