FPGA and digital SOIC SET’s control under heavy ion and proton irradiation

Abstract

The paper presents discussion about SETs generated in FPGA and SOIC under heavy ions and high energy protons irradiation and SET suppression in electronics. Schematic circuit for FPGA/SOIC SET detection is presented. The schematic circuit is designed for SET investigation both inside FPGA/SOIC and outside at package pin level. SET registration inside FPGA or SOIC is carried out as an event when logical cell is switched. Oscilloscope is used to register SETs at IC pin level. All SETs registered by oscilloscope are recorded and analyzed to collect data about SET amplitude and pulse width. The SET control schematic circuit was carried out at two different facilities: U400M heavy ion accelerator at the Joint Institute for Nuclear Research (JINR, Dubna, Russia) and picosecond PICO-3 laser facility (JSC «ENPO SPELS», Moscow, Russia). SET experimental results are presented and discussed in the paper.

Keywords

• VLSI
• FPGA
• SOIC